Recently, as flat panel displays are increased in size, the amount of data to be supplied to a display driver from a display controller increases. For example, for a UXGA (1920×1200) display, data need to be supplied to each pixel at the intervals of (1920+180)*(1200+300)*60 Hz=189 MHz (180 and 300 correspond to blanking intervals). Accordingly, the amount of data to be supplied to the display driver reaches 6.8 Gbit (189 MHz*12 bit*3(RGB)) per second.
As a high speed interface (IF) technique for the display driver, RSDS (Reduced Swing Differential Signaling) or Mini-LVDS (Low Voltage Differential Signaling) has been known. In the RSDS, data of about 170 Mbit is transmitted via bus-connected transmission paths having 12 to 15 channels. The Mini-LVDS is a data transmission scheme in which transmission paths of 3 to 6 channels are connected in a point-to-point manner, and data and a clock are supplied to a receiving side.
However, the RSDS has a problem in that, because impedance mismatching occurs at the bus-connected transmission paths, the transmission speed is limited by multi-reflection of signals. In addition, the Mini-LVDS has a problem in that the transmission speed is limited by the skew of the clock signal and the data signal that run parallel. Thus, in case of using such transmission methods, the number of channels should be increased for a large capacity, inevitably resulting in an increase in the costs of a transmission medium due to multi-layered substrate or the like.
In an effort to solve such problems, a clockless transmission using a clock and data recovery circuit has received much attention in the area of a high speed interfaces for display drivers.
FIG. 1 is a block diagram showing the configuration of a related clockless transmission system applied to an interface for a display driver. The clockless transmission system includes display controller 501, transmission medium 504, and display driver 506.
In FIG. 1, display controller 501 serializes image data and performs coding, such as 8B10B coding, to convert R, G, and B pixel data each having 8 bits into a 10-bit signal. Data transmission circuit 502 transmits general data obtained by multiplexing a clock signal through coding, as output signal 503, to transmission medium 504.
In display driver 506, clock and data recovery circuit 507 recovers the clock signal from the general data inputted as input signal 505 from transmission medium 504 and outputs the same, and separates the pixel data from the coded signal and outputs it. Display driving circuit 508 outputs the recovered clock signal and the separated pixel data to a display (not shown).
With such configuration, the skew problem of the clock signal and the pixel data signal is solved, enabling high speed signal transmission. In addition, because the number of channels can be reduced by serialization and high speed transmission, the clockless transmission expectedly allows reduction in the costs of the transmission medium.
However, when clock and data recovery circuit 507 in the clockless transmission system is applied to the interface for the display driver as shown in FIG. 1, clock and data recovery circuit 507 suffers from power supply noise that is generated by display driving circuit 508 of display driver 506.
FIG. 2 illustrates the operation of the clockless transmission system of FIG. 1, showing a phase relationship between the input signal and the recovered clock (half rate) before and after power supply noise.
In general, as shown in FIG. 2(a), the operation of display driver 506 is divided into data communication intervals, during which data to be displayed on a display is received, and into blanking intervals during which pixels of the received data are written in the display, which are repeated.
As shown in FIG. 2(b), display driving circuit 508 performs writing of the pixel data after one row of pixel data handled by display driver 506 is completely received. At this time, display driving circuit 508 consumes much current in writing the pixel data, generating much power supply noise.
Affected by the power supply noise, a clock phase of an oscillation circuit for generating the recovered clock included in clock and data recovery circuit 507 is greatly changed as shown in FIG. 2(c). Namely, before the power supply noise is generated, the input signal and the recovered clock are in synchronization, but after the power supply noise is generated, the input signal and the recovered clock are not synchronized any longer. This brings about an error, when a front bit of pixel data to be written on the display is received, after the blanking interval ends.
Over the problem, in an optical disk device disclosed in patent document 1, an error pattern detection circuit detects an error of a pattern length of recovered signal S1 read from an optical disk and outputs detect signal S2 indicating the amount of detection. A gain control circuit generates control signal S3 according to detect signal S2, and when the detection amount that is indicated by detect signal S2 is increased, the gain control circuit reduces an open loop gain of a PLL circuit. Through such operation, when the reliability of recovered signal S1 is low, the PLL circuit can hardly follow recovered signal S1 and jitter of the generated clock is restrained from increasing, and the PLL circuit supplies a stable clock, and thus, a decoding error of the recovered signal S1 is reduced.
In this manner, patent document 1 has as its object reducing the decoding error of the recovered signal resulting from a scar or dirt in the optical disk in the optical disk device.
However, patent document 1 does not disclose prevention of an error generated based on power supply noise in a clockless transmission system.
In a serial data receiving circuit disclosed in patent document 2, a PLL circuit generates a multi-phase clock from an input clock. An over-sample circuit over-samples input serial data during a blanking interval. A sampling clock selection circuit selects one sampling clock, given an optimum phase from among the multi-phase clocks generated by the PLL circuit, and captures data by single sampling using the selected single sampling clock during a non-blanking interval.
Patent document 2 describes the objective of seeking low power consumption and size reduction by accurately confirming data with the smaller number of samplings in the multi-channel high speed serial transmission system in which a timing skew is generated between channels.
However, patent document 2 does not disclose prevention of an error generated based on power supply noise in a clockless transmission system.
A light transmission apparatus disclosed in patent document 3 includes an FIFO for storing a plurality of digital image signals outputted from a host device, and a transmission means including a packet generator, a 8B10B encoder, and a light transmitter devised for reading the plurality of digital image signals stored in the FIFO in order, converting them into light signals, and sequentially transmitting the converted light signals to an image display device via a communication path formed of an optical fiber. The transmission means transmits the digital image signals stored in the FIFO during a period during which a horizontal synchronization signal for counting timing in a horizontal direction is to be transmitted to an image display device when the image display device draws a screen image. Accordingly, the transmission band can be reduced and the optical transmission system can be reduced in size.
In this manner, patent document 3 describes the objective of making the system small by narrowing the transmission band required for optically transmitting the digital signals.
However, patent document 3 does not disclose prevention of an error generated based on power supply noise in a clockless transmission system.
In a liquid crystal display system described in patent document 4, a PERSONAL COMPUTER makes a dot.clock.burst generated from a video signal output unit overlap with a horizontal synchronization signal, and supplies them as a composite synchronization signal to a liquid crystal display (LCD) device. The LCD device extracts the dot.clock.burst from the composite synchronization signal and reproduces a dot.clock based on the dot.clock.burst.
Patent document 4 describes the objective of supplying the signal for generating the dot.clock to a liquid crystal panel without the necessity of drastically changing the specification at the PERSONAL COMPUTER. Also, it describes the objective of simply generating the dot.clock at the liquid crystal panel and obtaining image display by using the stable liquid crystal panel without dot flickering or image shaking.
However, patent document 4 does not disclose prevention of an error generated based on power supply noise in a clockless transmission system.
In a PLL circuit described in patent document 5, the gain of a phase loop of a PLL that generates a clock signal such that it is synchronized with a color burst signal is controlled to be lowered during a vertical blanking period.
In this manner, patent document 5 describes the objective of restraining the frequency change of the clock signal generated during the period in which the color burst signal of the composite image signal does not exist, without delaying transitional clock pull-in, in the PLL circuit for receiving the color burst signal and the decoded image signal with the vertical blanking period, and extracting the clock signal in synchronization with the color burst signal.
However, patent document 5 does not disclose prevention of an error generated based on power supply noise in a clockless transmission system.
A PLL loop filter switching circuit disclosed in patent document 6 includes a plurality of NPN and PNP resistor-installed transistors operating as switches for switching a plurality of constants of a loop filter of a PLL circuit including a resistor and a capacitor for each input signal methods, and a logical circuit for determining conditions for case classifying. In this document, an input signal method is detected and the plurality of constant values of the PLL loop filter are automatically switched to optimum values for each condition.
In particular, patent document 6 describes the objective of minimizing clock jitter that significantly affects screen quality according to a target input signal, in case of a configuration in which analog RGB signals inputted from an external source are sampled to be controlled by an A/D converter that uses a signal generated in the PLL circuit as a clock.
However, patent document 6 does not disclose prevention of an error generated based on power supply noise in a clockless transmission system.
As described above, when the general clock and data recovery circuit is applied to the interface for the display driver, synchronization between the recovered clock of the clock and data recovery circuit and the input signal is lost due to power supply noise generated from the display driving circuit in the display driver.    Patent document 1: Japanese Laid Open Publication No. 2004-234808 (Claim 1, [0038], [0050], Claim 15))    Patent document 2: Japanese Laid Open Publication No. 2004-328063 ([0022], [0030])    Patent document 3: Japanese Laid Open Publication No. 2005-311879 ([0053]    Patent document 4: Japanese Laid Open Publication No. H9-044122 ([0013], [0018], FIG. 30)    Patent document 5: Japanese Laid Open Publication No. H09-182100 (Claim 1, FIG. 2, [0029])    Patent document 6: Japanese Laid Open Publication No. H10-178343 ([0019], Claim 1, [0019], [0024], Claim 4, [0018])